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r5402n101kd - 1/11 - product specifications R5402N101KD-TR-F contents [1] outline [2] block diagram [3] pin descriptions [4] absolute maximum ratings [5] electrical characteristics [6] test circuits [7] operation [8] technical notes [9] timing diagrams [10] package dimensions [11] mark specification
r5402n101kd - 2/11 - [1] outline the r5402n101kd is high voltage tolerance cmos- based protection ic for over-charge/discharge and over-current of rechargeable one-cell lithium-ion (li+)/lithium polymer battery. the r5402n101kd can detect over-charge/discharge of li+ one-cell and exce ss load current, further include a short circuit protector for preventing large external short circuit current and the excess charge-current. the r5402n101kd consists of four voltage detectors, a reference unit, a delay circuit, a short circuit detector, an oscillator, a counter, and a logic circuit. when the r5402n101kd detects over-charge or over-charge current, the output of c out pin switches to ?l? level, that is, the charger?s negative pin leve l after the internal fixed delay time. when the r5402n101kd detects over-discharge or ex cess discharge current, the output of d out pin switches to ?l? level after the internal fixed delay time. after detecting over-charge voltage or over-charge curren t, if the battery voltage is lower than over-charge detector threshold voltage, the r5402n 101kd can be reset and the output of c out becomes ?h? when a kind of load is connected to v dd after a charger is disconnected from the battery pack. if a charger is continuously connected to the battery pack, when the cell voltage becomes equal or lower than the release voltage from over-charge, over-charge will be released and c out becomes ?h?. after detecting over-discharge voltage, connect a charger to the battery pack, and when the battery supply voltage becomes higher than over-discharge detector th reshold, or the battery voltage becomes equal or more than the released voltage from over-dischar ge, the r5402n101kd is released and the voltage of d out pin becomes ?h?. if the battery discharges into 0v level, recharge current is accepted. once after detecting excess discharge-current or shor t circuit, the r5402n101kd is released and d out level becomes ?h? with detaching a battery pack from a load system. after detecti ng over-discharge, supply current is kept extremely low by halting internal circuits' operation. when the output of c out is "h", by setting the v- pin at equal or lower than the delay time shortening voltage (typ. -2.0v) , the output delay can be shortened. especially , the delay time of over charge detector can be reduced into approximately 1/60. thus, testi ng time of protector circuit board can be reduced. output type of c out and d out is cmos. [2] block diagram shor t de te cto r d out c out v- ?n scilla to r vd 1 vd 2 lev el shi f t vd 3 c ount er log i c circu it de la y log i c circu it v dd v ss ds circu it vd 4
r5402n101kd - 3/11 - [3] pin description pin no. symbol pin description 1 d out output of over-dischar ge detection, cmos output 2 v- charger negative input 3 c out output of over-charge detection, cmos output 4 nc no connection 5 v dd power supply pin. substrate level of the ic. 6 vss ground pin. (ground level of the ic) [4] absolute maximum rating topt=25 c, vss=0v item symbol ratings unit supply voltage v dd -0.3 to 12 v input voltage v- pin voltage v- v dd -35 to v dd +0.3 v output voltage c out pin voltage d out pin voltage v c out v d out v dd -35 to v dd +0.3 vss-0.3 to v dd +0.3 v v power dissipation p d 150 mw operating temperature topr -40 to 85 c storage temperature tstg -55 to 125 c
r5402n101kd - 4/11 - [5] electrical characteristics ? r5402n101kd unless otherwise provided, topt=25c item symbol conditions min. typ. max. unit note1 operating input voltage v dd 1 v dd - vss 1.5 5.0 v a minimum operating voltage for 0v charging vst voltage defined as v dd -v-, vdd-vss=0v 1.8 v a over-charge threshold voltage v det 1 r1=330 ? r1=330 ? , topt=-5 c to 55 c *note2 4.225 4.220 4.250 4.250 4.275 4.280 v v b b released voltage from over-charge v rel 1 r1=330 ? 4.000 4.050 4.100 v b output delay of over-charge tv det 1 v dd =3.6v 4.4v 0.7 1.0 1.3 s b release delay for vd1 tv rel 1 v dd =4.5v 3.6v 11 16 21 ms b over-discharge threshold v det 2 detect falling edge of supply voltage 2.438 2.500 2.562 v b released voltage from over-discharge v rel 2 detect rising edge of supply voltage 2.925 3.000 3.075 v c output delay of over-discharge tv det 2 v dd =3.6v 2.2v 14 20 26 ms d release delay for vd2 tv rel 2 v dd =3v, v-=3v 0v 0.7 1.2 1.7 ms d excess discharge-current threshold v det 3 detect rising edge of 'v-' pin voltage 0.185 0.200 0.215 v e output delay of excess discharge-current tv det 3 v dd =3.0v, v-=0v to 0.5v 8 12 16 ms f output delay of release from excess discharge-current tv rel 3 v dd =3.0v, v-=3v to 0v 0.7 1.2 1.7 ms f short protection voltage vshort v dd =3.0v 0.55 0.80 1.00 v f delay time for short protection tshort v dd =3.0v, v-=0v to 3v 230 300 500 s f reset resistance for excess current protection rshort v dd =3.6v,v- =1.0v 25 50 75 k ? f excess charge-current threshold v det 4 detect falling edge of 'v-' pin voltage -0.130 -0.100 -0.070 v f output delay of excess charge-current tv det 4 v dd =3.0v, v-=0v to -1v 5 8 11 ms g output delay of release from excess charge-current tv rel 4 v dd =3.0v, v-=-1v to 0v 0.7 1.2 1.7 ms g delay time shortening mode voltage v ds v dd =4.4v -1.4 -2.0 -2.6 v g nch on-voltage of c out v ol 1 iol=50 a, v dd =4.5v 0.4 0.5 v g pch on-voltage of c out v oh 1 ioh=-50 a, v dd =3.9v 3.4 3.7 v h nch on-voltage of d out v ol 2 iol=50 a, v dd =2.0v 0.2 0.5 v i pch on-voltage of d out v oh 2 ioh=-50 a, v dd =3.9v 3.4 3.7 v j supply current i dd v dd =3.9v, v- =0v 4.0 8.0 a k standby c u rrent i standby v dd =2.0v 1.2 2.0 a l ? : ?note1? indicates test circuits shown in next page. note2: considering of variation in process parameters, we compens ate for this characteristic related to temperature by laser-trim, however, this specification is guaranteed by design, not mass production tested.
r5402n101kd - 5/11 - [6] test circuits a b c os ci llo s c op e v- v dd d out c out v ss v v v e d v f v a g i v h v a j v a k v a l v a a v dd v- v ss c out v dd v- v ss c out v dd v- v ss d out v dd v- v ss d out v dd v- v ss d out v dd v- v ss c out v dd v- v ss c out v dd v- v ss c out v dd v- v ss d out v dd v- v ss v dd d out v- v ss
r5402n101kd - 6/11 - [7] operation ? vd1 / over-charge detector the vd1 monitors v dd pin voltage during charge. when the v dd voltage crosses over-charge detector threshold v det1 (typ. 4.250v), the vd1 can sens e over-charge and the output of c out pin becomes ?l? and stop charging by turning off the external nch-mosfet. after detecting over-charge, when the voltage of v dd pin is equal or less than the released voltage from over-charge (typ. 4.050v), or when the v dd voltage is less than the over-charge detector threshold, if the charger is removed and connect a load, vd1 is released, then the output level of c out becomes ?h? and by turning on the external nch-mosf et, the battery charger is ready to work again. when the input level of v dd pin is equal or more than over-charge detector threshold, and while a charger is disconnected from the battery pack, if a load system is connected to the battery pack, the output level of c out pin is ?l?. however, load current can be flown through a parasitic diode of an external nch-mosfet. then, when the voltage level of v dd pin becomes lower than over-charge detector threshold, the output level of c out pin becomes ?h?. output delay time for over-charge detect and releas ed over-charge is internally fixed respectively. although the v dd voltage goes up to a higher level than over-charge detector threshold within the output delay time (typ. 1s), vd1 would not work for detecting over-charge. if the action for vd1 to release is done and the condition returns to the initia l one within the output delay time (typ.16ms), vd1 cannot be released. a level shifter is built in a buffer driver for the c out pin, because of this, the ?l? level is equal to the voltage level of v- pin. the output type of c out pin is cmos type. (the output level is between v dd and v-.) ? vd2/over-discharge detector the vd2 monitors a v dd pin voltage during discharge. when the v dd voltage crosses the over-discharge detector threshold v det2 (typ. 2.50v) from a high level to a lower level than v det2 , the vd2 senses over-discharge and stop discharge by turning off an external nch-mosfet. to reset the vd2 with the d out pin level being ?h? again after detecting over-discharge, if v dd voltage is equal or less than over-charge detector threshold, a charge current flows through a parasitic diode of the external nch mosfet. after that, when v dd voltage is more than over-discharge threshold, d out pin becomes "h", and by tuning on the external nch mo sfet, discharge is possible. in the case that a charger is connected to the battery pack, and v dd level is more than over-discharge detector threshold, the output level of d out becomes ?h? immediately. without connecting a charger, if v dd pin voltage is equal or more than the released voltage from ove r-discharge (typ.3.0v), the output level of d out becomes ?h?. when a cell voltage is equal to 0v, connecting a charger to the battery pack makes c out pin become "h" and the system is allowable for charge while t he voltage of the charger is more than the maximum limit of the minimum operating voltage (vst) for 0v charge. an output delay for over-discharge detection is fi xed internally. (typ. 20ms) although the voltage of v dd becomes equal or less than over-discharge detec tor threshold and if it becomes higher than over-discharge detector threshold within output del ay time, over-discharge detector does not work. output delay time for release from over-di scharge is also set internally. (typ. 1.2ms) after detecting over-discharge by vd2, supply current would decrease, (v dd =2.0v, max. 2.0 a.) because unnecessary circuits are halted and being standby. the output type of d out pin is cmos type and its output level is in between v dd and v ss .
r5402n101kd - 7/11 - ? vd3/ excess discharge current de tector, short circuit protector while charge and discharge are acceptable with the batte ry pack, vd3 monitors the voltage level of v- pin. in the cause of such as the external short-ci rcuit, if the voltage level of v- pin may become equal or more than the excess discharge current threshol d (typ. 0.200v) and less than the short detector threshold (typ. 0.8v), the excess discharge current detector works. when the voltage level of v- pin becomes equal or more than short detector threshold voltage, the short circuit protector works and the output level of d out becomes ?l?, and by turning off an exte rnal nch mosfet, vd3 protects against flowing extremely large current into the circuit. an output delay time for the excess discharge current detector is internally fixed at 12ms typical. although the voltage of v- pin becomes equal or mo re than the excess discharge current threshold voltage and less than short detector threshold, if it becomes less than the excess current detector threshold voltage within the output delay time, the excess current detector does not work. output delay time for release from excess discharge current is also set internally (typ. 1.2ms). in terms of short circuit protector, output delay time is typically 300 s. the v- pin has a built-in pull down resistor, typ. 50k ? connected to the vss pin. after an excess discharge current or short circuit protection is detected, by removing a cause of excess current or external short circuit, the voltage level of v- is pulled down through the resistor for release from excess current to the vss leve l. then, when the voltage level of v- pin becomes equal or less than the excess current thres hold voltage, both protection circuits are released automatically. resistor for release from excess discharge current is active when excess discharge current or short circuit is detected. while charge and discharge are a cceptable for the battery pa ck, or normal mode, the resistor is inactive. output delay time for excess discharge current is necessarily set shorter than output delay time for over-discharge. therefore, if excess discharge current is detec ted, and at the same time, v dd pin voltage becomes lower than over-discharge detector th reshold level, excess discharge current detector is predominant. by disconnecting load from the battery pack, the battery pack is automatically released from excess current state. ? vd4/ excess charge-current detector while charge and discharge are acceptable with the battery pack, vd4 senses v- pin voltage. for example, if the battery pack is charged by an i nappropriate charger, excess current flows, then the voltage of v- pin becomes equal or less than excess charge-current detector threshold (typ. ?0.10v). then, the output of c out becomes ?l?, and protects against flow ing excess current in the circuit by turning off the external nch mosfet. output delay of excess charge current is internally fixed. (typ. 8ms) even the voltage level of v- pin becomes equal or lower than excess charge-current detec tor threshold, if the voltage is higher than the vd4 threshold within the delay time, excess charge-curr ent state is not detected. output delay time for release from excess charge current is also set internally. vd4 can be released by disconnecting a charger and setting a load. ? ds (delay shortening) function when the c out is "h", the o utput delay time of over-charge, over-discharge, and release from over-discharge can be shorter than those setting va lues by forcing equal or lower than the delay shortening mode voltage (typ. -2.0v) to v- pin.
r5402n101kd - 8/11 - [8] technical notes v dd v- c out d out v ss 0. 1 f 1k ? 330 ? r5402n r1 c1 r2 *r1 and c1 stabilize a supply voltage to the r5402. a recommended r1 value is equal or less than 1k ? . a large value of r1 makes detection voltage sh ift higher because of the conduction current flown in the r5402. further, to stabilize the operation of r5402, use the c1 with the value of 0.01 f or more. *r1 and r2 can operate as a current limit against setting cell reverse direction or applying excess charge voltage to the r5402. while small value of r1 and r2 may cause over power dissipation rating of the r5402, therefore a total of ?r1+r2? should be 1k ? or more. besides, if a large value of r2 is set, release from over-discharge by connecting a charger might not be possible. recommended r2 value is equal or less than 10k ? .
r5402n101kd - 9/11 - [9] timing diagrams (1) timing diagram of over-c harge voltage and over-charge current vdd v- cout char g e cur r e n t di sc h a rge c u rren t vd d vss vd d v- vd e t 3 vd e t 4 co n n ect ch arger co n n ect l o ad ch arger op en + c onne c t l o a d ov er-ch a rg e cu rren t 0 vd e t 1 tvd e t4 t t t t cha r ge / disch a rg e c u rrent tvrel4 tvd e t1 tvd e t1 tvrel1 tvrel1 vre l 1
r5402n101kd - 10/11 - (2) over-discharge, excess di scharge current, short circuit de t 2 v dd d out v dd v ss v- v dd v de t 3 v ss v de t 4 conn ect l o ad connec t charger tv re l2 tv det 2 charge / d i s c harge current ch ar g e c u rrent d i s c h ar ge c u rr ent 0 tv det 3 tv det 2 tv re l2 ex ce ss di s c harge current sh ort v s hor t ts ho r t tv re l3 op e n tv det 2 tv re l2 v re l 2 conn ect l o ad conn ect l o ad connec t charger op e n v
r5402n101kd - 11/11 - [10] package dimensions (sot23-6) 2.9 r 0.2 1.9 r 0.2 (0.95) (0.95) 64 12 3 1.6 +0. 2 -0.1 2.8 r 0.3 0.4 0.8 r 0.1 1.1 +0.2 -0. 1 0 a 0.1 0.15 +0. 1 -0. 0 5 u n i t :m m 0. 2 min. 5 +0. 1 -0 . 2 [11] mark specification cd : series code name } vc ef : lot number (alphanumeric serial number) 6 4 1 2 3 cdef 5

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